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RT7262A ? ds7262a-01 september 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. applications z distributive power systems z battery charger z dsl modems z pre-regulator for linear regulators general description the RT7262A is a synchronous step-down regulator with integrated power mosfets. it achieves 2a of continuous output current over a wide input supply range with excellent load and line regulation. current mode operation provides fast transient response and eases loop stabilization. fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. an adjustable soft-start reduces the stress on the input source at start-up. the RT7262A requires a minimal number of readily available external components, providing a compact solution. features z z z z z wide input range : 4.5v to 21v z z z z z adjustable output from 0.808v to 15v z z z z z 2a output current z z z z z 150m /60m internal power mosfet switch z z z z z internal compensation minimizes external parts z z z z z 500khz fixed switching frequency z z z z z synchronized external clock from 300khz to 2mhz z z z z z adjustable soft-start z z z z z cycle-by-cycle over current limit z z z z z thermal shutdown protection z z z z z available in sop-8 (exposed pad) and wdfn-14l 4x3 packages z z z z z rohs compliant and halogen free 2a, 21v 500khz synchronous step-down converter package type qw : wdfn-14l 4x3 (w-type) sp : sop-8 (exposed pad-option 2) RT7262A lead plating system z : eco (ecological element with halogen free and pb free) simplified application circuit vin en/sync gnd boot fb sw l r2 RT7262A c boot r t c in c out r1 vcc c c v in v out chip enable
RT7262A 2 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. wdfn-14l 4x3 sop-8 (exposed pad) pin name pin function 1 1 vin power input. vin supplies the power to the ic, as well as the step-down converter switches. drive vin with a 4.5v to 21v power source. bypass vin to gnd with a suitably large capacitor to eliminate noise on the input to the ic. 2, 3, 4, 5 2, 3 sw switch node. sw is the switching node that supplies power to the output. connect the output lc filter from sw to the output load. note that a capacitor is required from sw to boot to power the high side switch. 6 4 boot bootstrap for high side gate driver. connect a 100nf or greater capacitor from sw to boot to power the high side switch driver. 7 5 en/sync enable or external frequency synchronization input. for automatic start-up, connect the en/sync pin to vin with a 100k resistor. the switching frequency can be changed by an external clock applying to the sync pin. 8 6 fb feedback input. fb senses the output voltage via an external resistive voltage divider. the feedback reference voltage is 0.808v typically. 9 -- pgood power good indicator is an open drain output. the power good rising/falling threshold is 90%/70% of regulation output voltage. 10 -- ss soft-start control input. connect a capacitor from ss to gnd to set the soft-start period. 11 7 vcc bias supply. decouple with 0.1 f to 0.22 f capacitor between this pin and gnd. 12, 13, 15 (exposed pad) 8, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 14 -- agnd analog ground. connect this pin to the system ground in pcb layout. pin configurations sop-8 (exposed pad) (top view) marking information wdfn-14l 4x3 vin sw sw sw agnd gnd gnd ss vcc sw boot pgood en/sync fb 13 12 11 1 2 3 4 5 14 69 10 gnd 15 78 07 : product code ymdnn : date code RT7262Azqw 07 ym dnn RT7262Azsp : product number ymdnn : date code RT7262A zspymdnn RT7262Azsp vin sw sw boot gnd vcc en/sync fb gnd 2 3 4 5 6 7 8 9
RT7262A 3 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram for wdfn-14l 4x3 package for sop-8 (exposed pad) package regulator vin v a v c + - 1.2v shutdown comparator fb ss pgood en/sync vcc + - 1.7v 1a 3v 5k lockout comparator reference + - v c error amplifier + 10a + - 400k 30pf 1pf s q r driver - + current sense amplifier pwm comparator oscillator ramp generator sw boot gnd + - v a s q r driver - + current sense amplifier pwm comparator oscillator ramp generator regulator reference + - error amplifier sw boot fb en/sync vin + - gnd vcc + - 1.2v + - 1.7v 1a 3v 5k lockout comparator shutdown comparator 400k 30pf 1pf
RT7262A 4 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the RT7262A is a constant frequency, current mode synchronous step-down converter. in normal operation, the high side n-mosfet is turned on when the s-r latch is set by the oscillator and is turned off when the current comparator resets the s-r latch. while the high side n-mosfet is turned off, the low side n-mosfet is turned on to conduct the inductor current until next cycle begins. error amplifier the error amplifier adjusts its output voltage by comparing the feedback signal (v fb ) with the internal reference. when the load current increases, it causes a drop in the feedback voltage relative to the reference, the error amplifier's output voltage then rises to allow higher inductor current to match the load current. oscillator the internal oscillator runs at fixed frequency 500khz. in short circuit condition, the frequency is reduced to 150khz for low power consumption. internal regulator the regulator provides low voltage power to supply the internal control circuits and the bootstrap power for high side gate driver. enable the converter is turned on when the en pin is higher than 2v. when the en pin is lower than 0.4v, the converter will enter shutdown mode and reduce the supply current to be less than 1 a. soft-start (ss) an internal current source charges an internal capacitor to build a soft-start ramp voltage. the fb voltage will track the internal ramp voltage during soft-start interval. the typical soft-start time is 4ms. uv comparator if the feedback voltage (v fb ) is lower than 0.4v, the uv comparator will go high to turn off the high side mosfet. the output under voltage protection is designed to operate in hiccup mode. when the uv condition is removed, the converter will resume switching. thermal shutdown the over temperature protection function will shut down the switching operation when the junction temperature exceeds 150 c. once the junction temperature cools down by approximately 30 c, the converter will automatically resume switching.
RT7262A 5 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply voltage, vin ------------------------------------------------------------------------------------------- ? 0.3v to 26v z switch voltage, sw ------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z boot voltage, boot ------------------------------------------------------------------------------------------- (sw ? 0.3v) to (sw + 6v) z other pins -------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wdfn-14l 4x3 -------------------------------------------------------------------------------------------------- 1.667w sop-8 (exposed pad) ---------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) wdfn-14l 4x3, ja -------------------------------------------------------------------------------------------- 60 c/w wdfn-14l 4x3, jc -------------------------------------------------------------------------------------------- 7.5 c/w sop-8 (exposed pad), ja ----------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc ---------------------------------------------------------------------------------- 15 c/w z junction temperature ------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) z supply input voltage range, vin --------------------------------------------------------------------------- 4.5v to 21v z junction temperature range --------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics (v in = 12v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit shutdown current i shdn v en = 0 -- 0 1 a quiescent current i q v en = 2v, v fb = 1v -- 0.7 -- ma upper switch on resistance r ds(on)1 -- 150 -- m lower switch on resistance r ds(on)2 -- 60 -- m switch leakage i leak v en = 0v, v sw = 0v or 12v -- 0 10 a current limit i lim v boot ? v sw = 4.8v 3.9 5.5 -- a oscillator frequency f sw v fb = 0.75v 425 500 575 khz logic-high v synch 1.8 -- -- sync threshold voltage logic-low v syncl -- -- 0.4 v sync frequency range f sync 0.3 -- 2 mhz sync input current i sync v sync = 6v -- 1.5 2.5 a power good rising threshold -- 90 -- % power good falling threshold -- 70 -- % power good sink current capability sink 4ma -- -- 0.4 v
RT7262A 6 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit power good leakage current -- 10 -- na short circuit frequency v fb = 0v -- 150 -- khz maximum duty cycle d max v fb = 0.8v -- 90 -- % minimum on time t on -- 100 -- ns feedback voltage v fb 4.5v v in 21v 0.796 0.808 0.82 v feedback current i fb -- 10 50 na logic-high v ih 2 -- 5.5 en voltage logic-low v il -- -- 0.4 v v en = 2v -- 1 -- en current i en v en = 0v -- 0 -- a under voltage lockout threshold v uvlo v in rising 3.8 4 4.2 v under voltage lockout threshold hysteresis v uvlo -- 400 -- mv vcc regulator -- 5 -- v vcc load regulation i cc = 5ma -- 5 -- % soft-start period t ss c ss = 47nf -- 4.7 -- ms thermal shutdown threshold t sd -- 150 -- thermal shutdown hysteresis t sd -- 30 -- c note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT7262A 7 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit for wdfn-14l 4x3 package table 1. recommended components selection v out (v) r1 (k ) r2 (k ) r t (k ) l ( h) c ou t ( f) 5 75 14.46 0 4.7 22 x 2 3.3 75 24.32 0 3.6 22 x 2 2.5 75 35.82 0 3.6 22 x 2 1.8 5 4.07 30 2 22 x 2 1.5 5 5.84 39 2 22 x 2 1.2 5 10.31 47 2 22 x 2 1.05 5 16.69 47 1.5 22 x 2 vin en/sync gnd boot fb sw 5 6 1 2, 3 4 l 100nf r2 22f RT7262A 8, 9 (exposed pad) c boot r t c in c out r1 vcc 0.1f c c 7 v in v out chip enable for sop-8 (exposed pad) package vin pgood vcc boot fb sw 9 8 1 2, 3, 4, 5 6 l 100nf r1 r2 v out 22f v in RT7262A 11 c boot c out c in ss 10 r t c ss 47nf gnd 12, 13, 15 (exposed pad) en/sync agnd pgood r3 100k 0.1f c c 7 on/off 14
RT7262A 8 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. switching frequency vs. temperature 300 350 400 450 500 550 600 650 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (khz) 1 switching frequency vs. input voltage 400 425 450 475 500 525 550 4 6 8 10 12 14 16 18 20 22 input voltage (v) switching frequency (khz) 1 output voltage vs. output current 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 1.26 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 output current (a) output voltage (v) efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 output current (a) efficiency (%) reference voltage vs. temperature 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 -50-25 0 25 50 75100125 temperature (c) reference voltage (v) reference voltage vs. input voltage 0.785 0.790 0.795 0.800 0.805 0.810 0.815 0.820 0.825 4 6 8 10 12 14 16 18 20 22 input voltage (v) reference voltage (v) typical operating characteristics v out = 1.22v v in = 12v, v out = 1.22v v out = 1.22v, i out = 0a to 2a v in = 21v v in = 12v v out = 1.22v, i out = 0a to 2a v in = 12v v in = 21v
RT7262A 9 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. current limit vs. input voltage 0 2 4 6 8 10 4 6 8 10 12 14 16 18 20 22 input voltage (v) current limit (a) current limit vs. temperature 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 12v, v out = 1.22v time (1 s/div) output ripple voltage v out (50mv/div) v sw (10v/div) i l (2a/div) v in = 12v, i out = 2a time (1 s/div) output ripple voltage v out (50mv/div) v sw (10v/div) i l (1a/div) v in = 12v, i out = 1a time (100 s/div) load transient response v out (200mv/div) i out (1a/div) v in = 12v, v out = 1.22v, i out = 0a to 2a time (100 s/div) load transient response v out (100mv/div) i out (1a/div) v in = 12v, v out = 1.22v, i out = 1a to 2a
RT7262A 10 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (25ms/div) power off from vin v in = 12v, v out = 1.22v, i out = 2a v out (1v/div) v in (10v/div) i l (5a/div) v pgood (5v/div) time (50 s/div) power off from en v in = 12v, v out = 1.22v, i out = 2a v out (1v/div) v en (5v/div) i l (5a/div) v pgood (5v/div) time (2.5ms/div) power on from en v in = 12v, v out = 1.22v, i out = 2a v out (1v/div) v en (5v/div) i l (5a/div) v pgood (5v/div) time (5ms/div) power on from vin v in = 12v, v out = 1.22v, i out = 2a v out (1v/div) v in (10v/div) i l (5a/div) v pgood (5v/div)
RT7262A 11 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the ic is a synchronous high volta ge step-down converter that can support the input voltage range from 4.5v to 21v and the output current can be up to 2a. output voltage setting the output voltage is set by an external resistive divider according to the following equation : where v fb is the feedback reference voltage 0.808v (typical). the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. figure 1. output voltage setting external bootstrap diode connect a 100nf low esr ceramic capacitor between the boot pin and sw pin as shown in figure 2. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the ic. note that the external boot voltage must be lower than 5.5v. figure 2. external bootstrap diode soft-start for wdfn-14l package the RT7262Azqw (wdfn-14l package) contains an external soft-start clamp that gradually raises the output voltage. the soft-start timing is programmed by the external capacitor between ss pin and gnd. the chip provides an internal 10 a charge current for the external capacitor. if 47nf capacito r is used to set the soft-start, the period will be 4.7ms (typ.). soft-start for sop-8 (exposed pad) package the RT7262Azsp (sop-8 (exposed pad) package) contains an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. soft-start automatically begins once the chip is enabled. during so ft-start, the internal soft- start capacitor becomes charged and generates a linear ramping up voltage across the capacitor. this voltage clamps the voltage at the internal reference, causing the duty pulse width to increase slowly and in turn reduce the output su rge current. the typical soft-start time for this ic is set at 2ms. under voltage lockout threshold the ic includes an input under voltage lockout protection (uvlo). if the input voltage exceeds the uvlo rising threshold voltage (4.2v), the converter resets and prepares the pwm for operation. if the input voltage falls below the uvlo falling threshold voltage (3.8v) during normal operation, the device stops switching. the uvlo rising and falling threshold voltage includes a hysteresis to prevent noise caused reset. chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shutdown the device. during shutdown mode, the RT7262A quiescent current drops to lower than 1 a. driving the en pin high (2v < en < 5.5v) will turn on the device again. for external timing control, the en pin can also be externally pulled high by adding a r en resistor and c en capacitor from the vin pin (see figure 3). ?? + ?? ?? out fb r1 v = v1 r2 sw boot 5v 100nf RT7262A RT7262A gnd fb r1 r2 v out
RT7262A 12 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 6 shows the synchronization operation in startup period. when the en/sync is triggered by an external clock, the RT7262A enters soft-start phase and the output voltage starts to rise. during the soft-start phase region, the oscillation frequency will be proportional to the feedback voltage until it is higher than 0.7v. with higher v fb , the switching frequency is relatively higher. after startup period about 2ms, the ic operates with the same frequency as the external clock. power good output the power good output is an open-drain output and requires a pull up resistor. when the output voltage is lower than 70% of its set voltage, pgood will be pulled low. it is held low until the output voltage returns to within the allowed tolerances once more. during soft-start, pgood is actively held low and only allowed to transition high after soft-start is over and the output voltage has reached 90% of its set voltage. output under voltage protection (hiccup mode) for the ic, hiccup mode of under voltage protection (uvp) is provided. when the fb voltage drops below half of the feedback reference voltage, v fb , the uvp function will be triggered and the ic will shut down for a period of time and figure 6. startup sequence using external sync clock figure 3. enable timing control an external mosfet can be added to implement digital control on the en pin, as shown in figure 4. in this case, a 100k pull-up resistor, r en , is connected between v in pin and the en pin. mosfet q1 will be under logic control to pull down the en pin. figure 4. digital enable control circuit the chip starts to operate when v in rises to 4.2v (uvlo threshold). during the v in rising period, if an 8v output voltage is set, v in is lower than the v out target value and it may cause the chip to shut down. to prevent this situation, a resistive voltage divider can be placed between the input voltage and ground and connected to the en pin to adjust enable threshold, as shown in figure 5. for example, the setting v out is 8v and v in is from 0v to 12v, when v in is higher than 10v, the chip is triggered to enable the converter. assume r en1 = 50k . then, figure 5. resistor divider for lockout threshold setting where v ih(min) is the minimum threshold of enable rising (2v) and v in_s is the target turn on input voltage (10v in this example). according to the equation, the suggested resistor r en2 is 12.5k . operating frequency and synchronization the internal oscillator runs at 500khz (typ.) when the en/ sync pin is at logic-high level (>2v). if the en pin is pulled to low-level for 10 s above, the ic will shut down. the RT7262A can be synchronized with an external clock ranging from 300khz to 2mhz applied to the en/sync pin. the external clock duty cycle must be from 30% to 90%. vin vcc en/sync vout clk external clk 2ms 10s RT7262A en gnd v in r en c en en RT7262A en gnd v in r en1 r en2 RT7262A en gnd 100k v in r en q1 en en1 ih(min) en2 in_s ih(min) (r x v ) r = (v v ) ?
RT7262A 13 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. highest efficiency operation is achieved by reducing ripple current at low frequency, but it requires a large inductor to attain this goal. for the ripple current selection, the value of i l = 0.24(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 2 for the inductor selection reference and it is highly recommended to keep inductor value as close as possible to the recommended inductor values for each vout as shown in table 1. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? then recover automatically. the hiccup mode of uvp can reduce input current in short-circuit conditions. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. table 2. suggested inductors for typical application circuit component supplier series dimensions (mm) tdk vlf10045 10 x 9.7 x 4.5 tdk slf12565 12.5 x 12.5 x 6.5 taiyo yuden nr8040 8 x 8 x 4 input and output capacitors selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : this formula has a maximum at v in = 2v out , where i rms = i out / 2. this simple worst case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, one 22 f low esr ceramic capacitors are recommended. for the recommended capacitor, please refer to table 3 for more detail. out in rms out(max) in out v v i = i 1 vv ? table 3. suggested capacitors for c in and c out location component supplier part no. capacitance ( f) case size c in murata grm32er71c226m 22 1210 c in tdk c3225x5r1c226m 22 1210 c out murata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out murata grm32er71c226m 22 1210 c out tdk c3225x5r1c226m 22 1210
RT7262A 14 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, v out , is determined by : higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. thermal shutdown thermal shutdown is implemented to prevent the chip from operating at excessively high temperatures. when the junction temperature is higher than 150 c, the chip is shut down the switching operation. the chip is automatically re-enabled when the junction temperature cools down by approximately 30 c. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. out l out 1 viesr 8fc ?? ?? + ?? ?? figure 7. derating curve of maximum power dissipation 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 wdfn-14l 4x3 sop-8 (exposed pad) four-layer pcb for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-14l 4x3 package, the thermal resistance, ja , is 60 c/w on a standard jedec 51-7 four-layer thermal test board. for sop-8 (exposed pad) package, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-14l 4x3 package p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 7 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT7262A 15 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 8 (b). pcb layout guide for sop-8 (exposed pad) figure 8 (a). pcb layout guide for wdfn-14l 4x3 layout considerations follow the pcb layout guidelines for optimal performance of the ic. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` sw node is with high frequency voltage swing and should be kept at small area. keep analog components away from the sw node to prevent stray capacitive noise pickup. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the ic. ` connect all an alog grounds to a common node and then connect the common node to the power ground behind the output capacitors. ` an example of pcb layout guide is shown in figure 8 for reference. vin sw sw sw agnd gnd gnd ss vcc sw boot pgood en/sync fb 13 12 11 1 2 3 4 5 14 69 10 gnd 15 78 c in c boot v out c out gnd v out c ss r t r1 r2 l gnd place the input and output capacitors as close to the ic as possible. sw should be connected to inductor by wide and short trace and keep sensitive components away from this trace. place the feedback components as close to the ic as possible. c in c boot v out c out gnd v out r t r2 r1 l gnd place the input and output capacitors as close to the ic as possible. sw should be connected to inductor by wide and short trace and keep sensitive components away from this trace. place the feedback components as close to the ic as possible. vin sw sw boot gnd vcc en/sync fb gnd 2 3 4 5 6 7 8 9
RT7262A 16 ds7262a-01 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension w-type 14l dfn 4x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.900 4.100 0.154 0.161 d2 3.250 3.350 0.128 0.132 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018
RT7262A 17 ds7262a-01 september 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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